1. Field of the Invention
This invention relates to a semiconductor integrated circuit device and more particularly to a semiconductor integrated circuit device containing non-volatile memory transistors.
2. Description of the Related Art
A representative memory cell used in a non-volatile semiconductor memory device such as a NAND flash memory is described in a document 1 (R. Shirota).
In the document 1, the details of the development of products of 256-Mbit NAND flash memories using an STI (Shallow Trench Isolation) structure, particularly, for element isolation is described.
The memory cell unit described in the document 1 has a structure in which selection transistors are arranged on both sides of a plurality of series-connected memory cell transistors. The plurality of memory cell transistors are formed in respective element active regions. The element active regions are separated by element isolation regions such as STI regions and the element active regions and STI regions are formed to extend in parallel so as to configure a memory cell array.
Part of the floating gate layer of the memory cell transistor is formed to cover the STI region. The volume of the covering part contributes to an increase in the ratio of the capacitance between the floating gate layer and the channel region to the capacitance between the floating gate layer and the control gate layer, that is, a so-called “coupling ratio”.
In order to form the above memory cell transistor, it is necessary to form an extremely narrow slit-form pattern or so-called “slits” in the conductor layer used as part of the floating gate layer. FIG. 28 shows a step in which slits 103 are formed.
As shown in FIG. 28, conductive layers 104 are conductive material layers used as parts of the floating gate layers of memory cell transistors and the gates of selection transistors. Each of the slits 103 is formed in parallel with the STI region in a portion of the conductive layer 104 which lies on the STI region. The width of the slit is smaller than that of the STI region. By forming the slits 103 in the conductive layers 104, it becomes possible to separate the floating gate layers for the respective memory cell transistors.
In a normal NAND flash memory, memory cells are miniaturized by serially connecting a plurality of memory cell transistors and reducing the number of contacts between bit lines and memory cell units.
However, as shown in FIG. 29, if the number of memory cell transistors is reduced to as a small number as one or two, the distance DSG-SG between the gates of the selection transistors is relatively narrowed. If the distance DSG-SG is relatively narrowed, it becomes difficult to form the slits 103 in the conductive layers 104.
According to the document 1, it is described that the process of forming a region which is narrower than a region patterned by lithography can be realized by so-called spacer processing.
However, if the distance DSG-SG is narrowed, it becomes difficult to form the slit 103 having width sufficiently larger than the width of the element isolation region required in the memory cell unit when taking the processing conversion difference or the like into consideration. Further, when the width of the STI region and the width of the element activation region AA are determined based on the minimum processing dimension, it is difficult to form the slits 103 by use of a patterning process by exposure.
A case wherein the number of memory cell transistors in the memory cell unit is reduced is described in a document 2 (K. Imamiya, et al.), document 3 (Jpn. Pat. Appln. KOKAI Publication No. 2000-149581 (Sakui, et al.) and document 4 (G. Tao, et al.), for example.
In the document 2, for example, utilization of a memory cell transistor is reported when one memory cell transistor is provided. It is an EEPROM using a so-called three-transistor cell unit. In such a flash memory, the process for miniaturizing the same tends to be influenced by the above-described problems.
Therefore, as described in a document 5 (S. Aritome, et al.), a method of forming a floating gate layer in self-alignment with an STI region is proposed.
However, as described in the document 5, if the floating gate layer is formed in self-alignment with the STI region, portions used as parts of the gate layers of the selection transistors may be separated for each selection transistor like the portions used as the floating gates of the memory cell transistors.
(Reference Documents)
1. R. Shirota, “A Review of 256 Mbit NAND Flash Memories and NAND Flash Future Trend”, Non-Volatile Semiconductor Memory Workshop (=NVSMW) 2000 pp 22–31.
2. K. Imamiya, et al., “32 kbyte three-transistor flash for embedded applications using 0.4 μm NAND flash technology”, Non-Volatile Semiconductor Memory Workshop (=NVSMW) 2000 pp 78–80.
3. Jpn. Pat. Appln. KOKAI Publication No. 2000-149581. (U.S. Pat. No. 6,307,807 B1.)
4. G. Tao, et al., “Reliability aspect of embedded floating-gate non-volatile memories with uniform channel FN tunneling for both program”, Non-Volatile Semiconductor Memory Workshop (=NVSMW) 2001 pp 130–132.
5. S. Aritome, et al., “A 0.67 μm 2 SELF-ALIGNED SHALLOW TRENCH ISOLATION CELL (SA-STI CELL) FOR 3V-only 256 Mbit NAND EEPROMs” IEDM (1994) pp 61–64.